1. Field of the Invention
The present invention relates to an optical transceiver module which carries out high-speed transmission by using an optical transmission technology and which is applied to, for example, 10 Gbps Ethernet (registered trademark).
2. Description of Related Art
In recent years, high-speed high-capacity optical networks have been constructed in order to respond to increase in the information-carrying capacity of the Internet which is caused by the spread of the Internet. As standards for communication equipment for use in high-speed high-capacity optical networks, there has been provided the IEEE802.3ae standard which is a next-generation Ethernet (registered trademark) standard which is aimed to increase the information-carrying capacity of the Internet and which can be applied to connection with trunk networks. As movement toward commercial production of transceivers compliant with the IEEE802.3ae standard, MSAs (Multi Source Agreement: each of which is a formal decision which is made by a group of two or more companies so that they put transceivers into commercial production according to a set of specifications determined by the group) have been pursued. In accordance with an MSA, commonality of the package size of products, pin assignment, specifications, etc. is achieved. As specifications based on the IEEE802.3ae standard which are provided by MSAs, there have been provided XENPAK (the common specifications of optical connectors and optical transceivers which operate according to the protocol of 10 Gbps attachment unit interface), optical transceiver specifications XPAK and X2 which are derived from XENPAK, module downsizing specifications XFP, and so on.
An optical transceiver module which is compliant with the above-mentioned specifications is constructed as an interface module in which a conversion function of converting a light signal into an electric signal and vice versa, a transmitting circuit, a receiving circuit, a serializer (i.e., a parallel-to-serial conversion circuit), a deserializer (i.e., a serial-to-parallel conversion circuit), a clock recovery circuit, etc. are unified into a package, and is provided with a connector structure for facilitating connection with equipment that handles transmit data and received data. An example of the structure of this type of optical transceiver module is disclosed by patent reference 1.
In such a related art optical transceiver module, a PHY (i.e., a physical layer: which is the first-one of layers of the OSI layer model having a hierarchical structure, into which communication functions which are defined based on the ISO standards and which computers should have are dividedly assigned, and which defines a network physical connection and a transmission method) unit reads NVR data from a nonvolatile external storage (referred to as an EEPROM from here on), such as an EEPROM disposed in the module, by way of an I2C (International Institute for Communications) bus or the like when a system including the module is started up, and writes the NVR data into an NVR data register thereof so as to place itself in an initial state. The NVR data are data for initial setting (or initialization) which are stored in an NVR (non-volatile storage register, in this case, the above-mentioned EEPROM) which is defined by the XENPAK specifications. The I2C bus is a serial bus which is proposed by Phillips Corp., and connects between two or more pieces of equipment using lines via which a serial clock and two signals for serial data are respectively transmitted.
[Patent reference 1] JP,2004-153403,A
[Patent reference 2] JP,2001-320391,A
It is possible to replace the EEPROM into which the NVR data is written with a flash memory of a microcomputer which is used for the implementation of other functions in order to simplify the structure of the related art optical transceiver module. In this case, the microcomputer carries out processing based on software programs. It can be therefore expected that it takes a longer time for the microcomputer to start up than for the PHY unit which consists of an ASIC to start up after being reset. Therefore, when the PHY unit starts up and then reads the NVR data from the microcomputer after being reset, as before, since the microcomputer has not completed the startup processing yet, a communication error occurs in the I2C bus.
A method of using a reset signal in order to prevent malfunctions from occurring in network equipment is disclosed by, for example, patent reference 2. This method includes the steps of disposing a switching means for switching between the on and off states of connection between a communication control means and a network in a network control means, and causing the switching means to switch to the off state in response to a reset signal inputted for restart of the network equipment so as to prevent reception of any signal from any other network equipment at the time of the restart of the network equipment, thereby preventing malfunctions from occurring in the network equipment. However, malfunctions which are a target to be solved of the method disclosed by patent reference 2 and measures of preventing the occurrence of those malfunctions differ from those of the present invention.